Optimizing Superconducting Erasure Qubit Designs for Erasure Advantage

Computational analysis of five dual-rail erasure qubit architectures for surface code error correction

Key Results Summary

0.1204
Best Threshold (Dimon)
2.3950
Best Scaling Exponent (Cavity QED)
12.64x
Max Optimization Improvement (Qutrit)
291
Physical Qubits (d=7, all architectures)

Surface Code Threshold by Architecture

Logical Error Rate vs Erasure Fraction (d=7)

Scaling Exponents (p=0.005)

Infrastructure Comparison

Architecture Comparison Table

Architecture Threshold Scaling Exp. Baseline p_L Optimized p_L Improvement Cycle Time (us)
Coupled Transmon 0.0205 1.8970 4.03e-7 1.36e-7 2.97x 0.74
Dimon 0.1204 2.2326 5.32e-8 1.38e-7 0.39x 0.62
Cavity QED 0.1078 2.3950 2.12e-8 1.37e-7 0.16x 1.60
Qutrit 0.0000 1.6715 1.71e-6 1.35e-7 12.64x 0.60
Fluxonium 0.0679 2.0989 1.18e-7 1.36e-7 0.87x 1.60